library verilog;
use verilog.vl_types.all;
entity pmi_counter is
    generic(
        pmi_data_width  : integer := 8;
        pmi_updown      : string  := "up";
        pmi_family      : string  := "EC";
        module_type     : string  := "pmi_counter"
    );
    port(
        Clock           : in     vl_logic;
        Clk_En          : in     vl_logic;
        Aclr            : in     vl_logic;
        UpDown          : in     vl_logic;
        Q               : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_data_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_updown : constant is 1;
    attribute mti_svvh_generic_type of pmi_family : constant is 1;
    attribute mti_svvh_generic_type of module_type : constant is 1;
end pmi_counter;
